Generally, computer programs are initially written in high level program statements. In order to be executed by a computer, the program statements are compiled into machine instructions that a microprocessor can recognize and execute. The machine instructions are selected from a set of machine instructions unique to a particular instruction set architecture (ISA).
Computer program statements that have been decoded into machine instructions for a source ISA such as Intel® X86, may undergo a binary translation in order to be executed at a target ISA, such as a reduced instruction set computer (RISC) architecture, or a very long instruction word (VLIW) architecture.
The translation may be performed by a dynamic translator, typically stored in memory. During translation, instructions are typically translated one basic block of instructions (BB) at a time and stored in memory. For example, each basic block of instructions may include a contiguous sequence of non-branch instructions (i.e., do not change order of executing instructions) which typically ends with a branch instruction.
Unfortunately, translated executable (binary) applications are generally not optimized in order to take advantage of the various optimization techniques provided by the target ISA. The performance of the target ISA is often a function of how well the processor manipulates and controls the flow of data within the system. As such, a target ISA can generally provide increased speed and throughput of instructions executed by the processor, as a result of several decades of engineering and research for optimizing instruction execution and data throughput as compared to a legacy (source) ISA. For example, the processors of the target ISAs achieve increased performance by executing instructions out of their original program order. By scheduling instructions according to availability of machine resources the processor is allowed to take advantage of parallelism inherent in the code.
Unfortunately, optimization of translated code is generally prohibited since the translation is generally limited to execution of translated instructions according to the program order provided in the source binary application. Otherwise, it may be difficult to determine a source ISA application state, according to a current target ISA application state. Furthermore, a single source or legacy instruction may be translated into several target ISA instructions. As a result, it is often difficult to determine correspondence between a target ISA application instruction and a source ISA application instruction.
Hence, the fact that instructions, such as load, store and floating point instructions may cause exceptions generally prohibits dynamic binary translation (DBT) optimizations. This challenge is posed due to the fact that native instructions in a translated region may generate exceptions.
Supporting such enabling exceptions is essential to provide full binary compatibility in a DBT system. On the other hand, straightforward recovery of such exceptions may severely constrain optimizations. For example, it may not be possible to move an update of a register past an exception instruction because doing so may change the machine state, as seen by, for example, an exception handler. As another example, reordering of loads that may cause segmentation errors is prohibited because reordering changes the order of exceptions raised by exception instructions.